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Reconfigurable computing is a rapidly evolving field of computer science that uses Field Programmable Gate Arrays (FPGAs) to implement high-performance co-processing elements for application acceleration. FPGAs are reconfigurable logic devices that may be configured to instantiate complex special-purpose processing functions exhibiting hybrid characteristics that combine the flexibility of software and the performance of an application specific integrated circuit (ASIC).
FPGAs are well suited for text, data and integer processing algorithms where acceleration factors of 100x to 1000x over conventional microprocessors and be achieved. The extremely low power requirements of FPGAs and support for rapid reconfiguration make the technology ideal for field-deployable computing resources.
Brown Deer Technology has years of experience supporting conventional EDA workflows for FPGA application development. Brown Deer also develops powerful integrated software allowing programmers to access FPGA-based co-processing through compilers within a familiar UNIX-based development environment.
Reconfigurable Computing Workflow for Programmers. Access to the capabilities of FPGA co-processors has been greatly limited to engineers familiar with conventional digital circuit design techniques. True reconfigurable computing requires access to the FPGA through a development environment familiar to computer programmers.
Using a compiler-based workflow, programmers can develop applications using a high-level language such as C or FORTRAN. The high-level language (HLL) is transformed into an intermediate representation (IR) for optimization and refinement and converted into an assembly language (ASM) representation targeting a virtual instruction set architecture (vISA). An assembler is then used to construct the logical circuit instantiating the application in a hardware description language such as VHDL or Verilog. In the final step, back-end synthesis tools are used to generate a binary image for configuring the FPGA, which may be encapsulated into a linkable object file (OBJ). The open workflow allows for the incorporation of application specific extensions and hard-coded IP cores.
Virtual Instruction Set Architecture (vISA). A virtual instruction set architecture (vISA) is a virtualized processor architecture used to create a convenient target language for compilers supporting FPGA-based application development.
The vISA closely resembles the ISA of a conventional microprocessor with extensions to support the unique capabilities of FPGAs. The effect is to create a reconfigurable processor in the form of virtualized hardware since no actual stored-instruction processor exists.
An assembler is used to instantiate a hybridization of a dataflow and finite state machine implementation of the application-specific algorithm. The assembler can be made to exploit instruction-level and task parallelism, instruction predicates and pipelining. The result from the programmer's perspective is the capability of generating highly-optimized application-specific reconfigurable processors resembling a RISC-like many-core architecture.
UNIX-Based Process Management. In order to create an environment more familiar to programmers and software engineers, UNIX semantics and extensions can be used to unify software and hardware processes.
Creating a user/kernel interface for hardware processes that closely resembles that found on UNIX-based platforms provides a unified environment for application development. Kernel services can be provided for hardware processes running on an FPGA similar to the services provided to a conventional software process. In this way reconfigurable computing resources are managed like any other resource within the system.
The host operating system can be modified to provide process control (creation, scheduling, and termination) as well as utilities like a loader for hardware process binaries (FPGA bitstreams). These additional kernel services can be added through the system call API and the specifics of a particular reconfigurable architecture can be abstracted away using subsystem interfaces similar to those of conventional device drivers.
The host operating system can be extended into the reconfigurable device, creating the equivalent of a hardware operating system. The benefits of extending kernel services to the reconfigurable device include support for unified memory management, signaling and file I/O. User hardware processes can be isolated from complexity by introducing a hardware system library (stdlib for hardware).